The present disclosure relates to semiconductor devices and methods of fabricating the same, and in particular relates to magnetic memory devices and methods of fabricating the same.
Magnetic memory devices are typically defined, for example, as electronic components storing data in a nonvolatile capacity, and which include magnetic tunnel junction (MTJ) structures in which the resistance value varies according the magnetization direction on magnetic layers. Moreover, there is an increasing demand for magnetic memory devices because of, for example, their ability to operate at high frequencies and their re-writing properties. For example, an MTJ configuration may be composed of, two magnetic layers and a tunneling barrier layer interposed between the magnetic layers. The resistance value of the MTJ structure when the magnetization direction of each of the two magnetic layers are arranged in the same direction may be smaller than the resistance value for the MTJ structure when the magnetization direction of the two magnetic layers are aligned in reverse directions to each other. Furthermore, the magnetization direction of each of the above two magnetic layers may be stored as information data in the MTJ as logical values “1” or “0”.
Typically, a magnetic memory cell having a MTJ structure is arranged by being connected to bit and digit lines. Such a magnetic memory cell is illustrated as follows.
FIG. 1 is a sectional view showing a conventional magnetic memory device. Referring to FIG. 1, a lower interlevel oxide film 2 is disposed on a semiconductor substrate 1 and a digit line 3 is arranged on the lower interlevel oxide film 2. An intermediate interlevel oxide film 4 covers the digit line 3 and the lower interlevel oxide film 2. A lower plug 5 penetrates the intermediate and lower interlevel oxide films 4 and 2 in sequence to be connected to the semiconductor substrate 1. The lower plug 5 is laterally isolated from the digit line 3. The lower plug 5 is connected to source/drain regions of a MOS transistor (not shown) formed in the semiconductor substrate 1.
A cell electrode 6 is disposed on the intermediate interlevel oxide film 4. The cell electrode 6 meets with an upward face of the lower plug 5 and then laterally extends to cover the digit line 3. The cell electrode 6 is insulated from the digit line 3 through the intermediate interlevel oxide film 4.
An MTJ structure 10 is disposed on the cell electrode 6. The MTJ structure 10 is aligned to overlap with the digit line 3. The MTJ structure is composed of a first magnetic layer 7, a tunnel barrier 8, and a second magnetic layer 9. The first magnetic layer 7 is fixed in the direction of the magnetization moment. However, the second magnetic layer 9 may be varied by an external electric field.
Moreover, an upper interlevel oxide film 11 covers the cell electrode 6 and the MTJ structure 10. An upper plug 12 penetrates the upper interlevel oxide film 11, which is connected to the MTJ structure 10. A bit line is interposed on the upper interlevel oxide film 11, crossing over the digit line 3. The bit line 13 is connected with the upper plug 12. The bit line 13 is aligned to overlap with the MTJ structure 10. In other words, the MTJ 10 structure is interposed between the digit line 3 and the bit line 13, which intersect with each other. Here, the MTJ structure is electrically connected to the bit line 13 but insulated from the digit line 3. The bit line 13, the MTJ structure 10, the cell electrode 6, and the lower plug 5 form a current path to read out a data bit.
A unit cell of the magnetic memory device is comprised of the MTJ structure 10, and the digit and bit lines 3 and 13. The digit line 3 is shared by pluralities of unit cells that are arranged in parallel, while the bit line 13 is shared by pluralities of unit cells that are arranged in parallel with the pluralities of the bit lines. In a cell array of the magnetic memory device, pluralities of the digit lines 3 are arranged in parallel along a direction and the pluralities of the bit lines 13 cross over the digit lines 3 in parallel.
The above-mentioned conventional magnetic memory device is programmed through an electric field as a vector sum of a first electric field induced by the digit line 3 and a second electric field induced by the bit line 13. Namely, the vector-summed electric field programs a data bit into a selective one among the pluralities of the MTJ structures 10 arranged in a second-dimensional pattern. When programming data according to the above conventional manner, the digit line 3, the MTJ structure 10, and the bit line 13 should be efficiently aligned or arranged.
However, it may be difficult to accomplish an efficient arrangement among the MTJ structure 10 and the digit and bit lines 3 and 13. For example, a way of arranging the MTJ structure 10 and the digit and bit lines 3 and 13 may be carried out such that after aligning the MTJ structure 10 to the digit line 3, the bit line 13 is aligned to the MTJ structure 10. Nevertheless, with the above conventional approach, there still may be difficulties in achieving an alignment among the MTJ structure 10 and the lines 3 and 13 because of a coupling effect which may occur between the MTJ structure 10 and the digit line 3 and between the bit line 13 and the MTJ structure 10. The above-mentioned alignment difficulty may result in deviations occurring among the unit cells arranged in second-dimensional patterns. Such alignment deviations may increase as the magnetic memory device become more highly integrated, which in turn may cause program disturbance such as the program failure of selected cells or data changes of deselected cells. Consequently, the above program disturbance may result in an increase in the defect rate of the magnetic memory device.
Thus, there is a need for a magnetic memory device which minimizes the occurrence of program disturbance and for a method of forming the same.